37e12036

By: Tom Sydney Kerckhove <syd@cs-syd.eu>

Compile each dead-disable module on its own, and cover the two missing verdicts

Total

18m14s

Created Started Finished

Time to Start Worker time Duration Time to finish Idle
Config 3s 0s 0s 4s 3s
Eval 6s 20s 20s 26s 1s
Build 26s 26s 17m52s 18m18s 17m27s
Suite 3s 47s 18m14s 18m18s 17m32s

Timeline

Config Eval Build Compressed gap
0s10s20s18m18m10s